Conventionally, when a power-amplifying radio frequency signal such as a CDMA signal or a multi-carrier signal is amplified, a distortion compensation unit is added to a common amplifier, so that an operating range of the common amplifier can be expanded to include a saturation region to achieve a low power consumption. Although there are distortion compensation methods such as a feed-forward distortion compensation or a predistortion compensation, such methods have limitations to achieve the low power consumption. Therefore, Doherty amplifiers are recently attracting attentions as a candidate for a high efficiency amplifier.
FIG. 1 shows a configuration diagram of a conventional Doherty amplifier. A signal inputted to an input terminal 1 is divided by a divider 2. One of the divided signals is inputted to a carrier amplifying circuit 4. The carrier amplifying circuit 4 includes an input matching circuit 41 for implementing impedance matching to an input side of an amplifying device 42; the amplifying device 42, which contains, e.g., one or more transistors; and an output matching circuit 43 for implementing impedance matching to an output side of the amplifying device 42. A λ/4 transformer 61 is connected to an output terminal of the carrier amplifier 4 to transform an output impedance thereof.
The other divided signal is inputted to a peak amplifying circuit 5 after its phase is delayed by 90° by a phase converter 3. Similarly to the carrier amplifying circuit 4, the peak amplifying circuit 5 includes an input matching circuit 51; an amplifying device 52 containing, e.g., one or more transistors; and an output matching circuit 53.
An output signal of the λ/4 transformer 61 is combined with that of the peak amplifying circuit 5 at a summing node 62. The combined signal is transformed by a λ/4 transformer 7 such that an output impedance of the amplifier is matched to an output load 9, i.e., Z0. The combination of the λ/4 transformer 61 and the summing node 62 is referred to as a Doherty combiner 6. An output of the λ/4 transformer 7 is applied via an amplifier output terminal 8 to the output load 9.
The carrier amplifying circuit 4 and the peak amplifying circuit 5 differ in that the amplifying device 42 is biased in class-AB whereas the amplifying device 52 is biased in class-B or class-C. Therefore, the amplifying device 42 operates alone until an input level of the amplifier reaches a region where it begins to be saturated and the amplifying device 52 starts to operate. That is, the amplifying device 52 starts to operate when a linearity of the amplifying device 42 starts to be rapidly deteriorated, so that an output signal of the amplifying device 52 is applied to the load to drive it together with the amplifying device 42. At this time, although a load line of the output matching circuit 43 moves from a high resistance to a low resistance as will be described later, the efficiency of the amplifying device 42 is high because the amplifying device 42 is in its saturation region.
When an input level from the input terminal 1 to the amplifier further increases, the amplifying device 52 also starts to be saturated. However, the efficiency of the amplifier remains to be high even at this time, because both the amplifying devices 42 and 52 are saturated.
FIG. 2 illustrates theoretically predicted values of a collector efficiency or drain efficiency of the Doherty amplifier shown in FIG. 1. The collector efficiency is defined as a radio frequency output power outputted by a collector of an amplifying transistor divided by a product of a DC voltage applied from a power supply to the collector and a DC current supplied from the power supply. Likewise, the drain efficiency is defined as a radio frequency output power outputted by a drain of an amplifying transistor divided by a product of a DC voltage applied from a power supply to the drain and a DC current supplied from the power supply.
The horizontal axis of the FIG. 2 represents an amplifier back-off, i.e., a dB ratio between a compression point and an input level of the amplifier when the compression point is set to be 0 dB, wherein the compression point is defined as a minimum input level for both the amplifying devices 42 and 52 to be saturated.
In FIG. 2, a dashed line represents the efficiency of a conventional class-B amplifier and a solid line represents the efficiency of a Doherty amplifier shown in FIG. 1.
When the input level of the amplifier is within a range A, the carrier amplifying circuit basically operates alone. When the amplifier back-off reaches about 6 dB, the carrier amplifying circuit 4 starts to be saturated and the efficiency of the Doherty amplifier reaches about a maximum efficiency of the conventional class-B amplifier. At this time, an output power of the carrier amplifying circuit 4 is about Po/4, wherein Po is a maximum output power of the Doherty amplifier.
In a range B where the amplifier back-off is between 0 dB and 6 dB, as the input level of the Doherty amplifier increases, the output power of the carrier amplifying circuit 4 increases from about 0.25Po to about 0.5Po and an output power of the peak amplifying circuit 5 increases from 0 to 0.5Po. Further, in the range B, the sum of the output power of the carrier amplifying circuit 4 and that of the peak amplifying circuit 5 is proportional to the input power of the Doherty amplifier with a same proportional constant as that of the range A. When the peak amplifying circuit 5 starts to operate, the efficiency of the Doherty amplifier decreases temporarily a little bit. However, the efficiency of the Doherty amplifier starts to increase again, so that it reaches its peak at the compression point where the peak amplifying circuit 5 starts to be saturated. At the compression point, the output power of the carrier amplifying circuit 4 is substantially equal to that of the peak amplifying circuit 5.
In general, CDMA signals and multi-carrier signals have a high peak factor, i.e., a ratio between the peak power and the average power. However, a conventional amplifier has an operating point below the compression point in order to correspond to a peak factor ranging from 7 dB to 12 dB.
In the following, components in the Doherty amplifier and their impedance will be described with reference to FIG. 1. Since the impedance of the output load Zo is a constant, it is set to be a reference value. If we let the input impedance of the λ/4 transformer 7 seen from the node 62 be defined as Z7 and the characteristic impedance of the λ/4 transformer 7 be defined as Z2, the following equation is established:
                              Z          7                =                              Z            2            2                                Z            O                                              Eq        .                                  ⁢        1            
Thus, Z4, which is the input impedance of the λ/4 transformer 61 seen from the output matching circuit 43, can be obtained as follows. In the range A, since the output impedance of the output matching circuit 53 is practically infinite, Z4 and Z5 can be obtained by following equations:
                              Z          4                =                                            Z              1              2                                      Z              7                                =                                                    Z                1                2                                            (                                                      Z                    2                    2                                    /                                      Z                    O                                                  )                                      =                                          Z                O                            ⁢                                                Z                  1                  2                                                  Z                  2                  2                                            ⁢                                                          ⁢                              (                                  in                  ⁢                                                                          ⁢                  range                  ⁢                                                                          ⁢                  A                                )                                                                        Eq        .                                  ⁢        2                                          Z          5                =                  ∞          ⁢                                          ⁢                      (                          in              ⁢                                                          ⁢              range              ⁢                                                          ⁢              A                        )                                              Eq        .                                  ⁢        3            
wherein Z1 is the characteristic impedance of the λ/4 transformer 61.
However, in a range C where the input level is higher than the compression point, Z7 can be regarded as a parallel pair of the output impedance of the λ/4 transformer 61 seen from the node 62 and the output impedance of the output matching circuit 53, wherein said output impedances are equal. Therefore, in the range C, Z4 and Z5 can be obtained as:
                              Z          4                =                                            Z              1              2                                      2              ⁢                              Z                7                                              =                                    1              2                        ⁢                          Z              O                        ⁢                                          Z                1                2                                            Z                2                2                                      ⁢                                                  ⁢                          (                              in                ⁢                                                                  ⁢                range                ⁢                                                                  ⁢                C                            )                                                          Eq        .                                  ⁢        4                                          Z          5                =                  2          ⁢                      Z            7                    ⁢                                          ⁢                      (                          in              ⁢                                                          ⁢              range              ⁢                                                          ⁢              C                        )                                              Eq        .                                  ⁢        5            
In the range B, Z4 and Z5 vary within the limits of those in the ranges A and C.
The above result can be interpreted as follows. When the Doherty amplifier is applied in a high frequency operation, the value of Z4 for a case when the input level is relatively high, i.e., in the range C, is half as large as that of Z4 for a case when the input level is relatively low, i.e., in the range A. For example, if Z7=25Ω and Z1=50Ω, Z4 varies in the range of 100-50Ω. Thus, the impedance of the amplifying device 42 also varies pursuant thereto.
Besides the conventional Doherty amplifier described above, there is known a modified Doherty amplifier capable of compensating the deterioration of its characteristics by controlling a gate bias voltage based on a drain current (for example, see Japanese Patent Laid-open Application No. 2004-260232).
Further, there is also known a modified Doherty amplifier in which all amplifying circuits are configured in two or more stages (for example, see Japanese Patent Laid-open Application No. 2004-173231).
Still further, there is also known a modified Doherty amplifier in which all harmonic components are combined to be cancelled out (for example, see Japanese Patent Laid-open Application No. H6-82998).
However, when the conventional Doherty amplifier is applied in a high frequency operation by using a semiconductor amplifying device, the impedance seen from the amplifying device 42 cannot be easily adjusted to make it agree with the value obtained based on Doherty theory because the load line seen from the amplifying device 42 varies in accordance with the behavior of the output matching circuit 43.
FIG. 3 is a Smith chart representing an exemplary variation of the load impedance. ZA, ZB and ZC are load impedances of the amplifying device 42. These impedances are between 2Ω and 20Ω or less, noticeably small compared to Z4, and not purely resistive. This Smith chart is normalized by a resistance arbitrarily chosen between ZA and Z4. Three closed curves including ZA in their central portion are constant output power curves respectively representing 0.9 P, 0.5 P and 0.25 P, which show that the output power decreases as impedance matching becomes inaccurate. As shown therein, the maximum output power P can be obtained when the load impedance of the amplifying device 42 is ZA.
Further, four dotted curves crossing the constant output power curves are constant efficiency curves respectively representing efficiencies a, b, c, and d, that decrease in this order.
The output matching circuit 43 transforms the load impedance of the amplifying device 42 into Z4, i.e., the input impedance of the λ/4 transformer 61. The output matching circuit 43, if configured as a lumped element circuit, transforms an impedance pursuant to a constant resistance circle or constant conductance circle on the Smith chart. Although FIG. 3 depicts only two dashed curves as exemplary impedance transformation paths for simplicity, the actual paths of impedance transformation can be varied arbitrarily.
Since Z4 decreases from ZoZ12/Z22, i.e., Z4(A), to ZoZ12/2Z22, i.e., Z4(C), as the input level increases, if Z4(C) is matched to ZA for obtaining the maximum output power in the range C, Z4(A) is matched to ZB. However, considering that any impedance will result in an output power of 0.25Po as long as the impedance varies on the constant output power curve corresponding to 0.25Po, it is to be noticed that the case of matching to ZC is superior in efficiency to the case of matching to ZB. That is, the amplifying device 42 operates most efficiently when the load impedance of the amplifying device 42 is transformed from ZC into ZA as the input level increases.
The above description is for the case where only output power and efficiency are taken into consideration. However, in general, a performance of an amplifier is described not only by output power and efficiency but also by gain and distortion. Even considering such impedance matching that satisfies specified conditions on output power, efficiency, gain and distortion of a specified kind of the amplifying device 42, there are some cases where it is more preferable that the load impedance of the amplifying device 42 varies outwardly than inwardly with respect to the center of the Smith chart as the input level increases. Further, there are also cases where it is preferable that the impedance varies to ZA from an arbitrary point having good characteristics.
However, sometimes it is difficult for a conventional matching circuit to transform Z4, which varies inwardly with reference to the center of the Smith chart, into an impedance which varies outwardly with reference to the center of the Smith chart so that the two dashed curves representing the impedance transformation paths in FIG. 3 can cross each other. Therefore, in the conventional Doherty amplifier, the output matching circuit 43 can only implement such impedance matching as the impedance varies between ZB and ZA, thereby imposing a limitation in enhancing the performance.
Further, in the conventional Doherty amplifier, when connecting plural amplifiers serially to implement a high-gain common amplifier, the dividing loss in the divider 2 becomes high and the power efficiency or the power added efficiency becomes low.
FIG. 10 is a configuration diagram of a conventional two-stage common amplifier. A signal amplified by a preamplifier 20 is divided into two signals by the divider 2 in a manner that the divided signals have a same efficiency, which means an occurrence of 3 dB loss. That is, since the input impedance varies pursuant to the input level in a complicated way, it is not possible for all the electric powers of the divided signals to be used effectively.
At least, within the range A, all the electric power distributed to the peak amplifying circuit 5 is dissipated. That is, most part of the electric power distributed to the peak amplifying circuit 5 is reflected, and the reflected waves are usually dissipated in, e.g., an isolator (not shown), or, if the divider 2 is Wilkinson type, in a dummy resistor (not shown). Further, within the range B, the electric power distributed to the peak amplifying circuit 5 is partly reflected. However, since the output power of a class-B or class-C amplifying circuit increases gradually and the reflection power decreases, the summation at the node 62 in FIG. 10 can be performed while the gain of the range A (that is, the linearity) is maintained.
Therefore, we need to take the above-mentioned loss about 3 dB, which will be referred to as “dividing loss,” into account.
FIG. 11 presents a graph depicting the normalized input power and the output powers of the carrier amplifier 4, the peak amplifier 5 and both. FIG. 11 also shows an assumed output power of the carrier amplifier 4 as a single body in case of the dividing loss being zero. As shown therein, the output power of the peak amplifying circuit 5 increases rapidly in the vicinity of the amplifier back-off of 6 dB, so that, within the range B where the amplifier back-off is 6 dB or less, the carrier amplifying circuit 4 takes a share of the load together with the peak amplifying circuit 5. Further, we can see that, e.g., the gain is reduced significantly due to the dividing loss compared to a carrier amplifying circuit as a single body.
Hereinafter, it will be described how the power added efficiency of the common amplifier is calculated in case practical specifications of the preamplifier 20 and the Doherty amplifier 10 are assumed. The amplifier back-off is set to be a standard value (7 dB to 10 dB) so that the input power of the peak amplifying circuit 5 is dissipated sue to the reflection, and the preamplifier 20 is chosen to be a conventional class-AB amplifier instead of being the Doherty amplifier.
The specification of the Doherty amplifier 10 is as follows:
output power; 20 W
gain; 9 dB (including the dividing loss)
collector efficiency; 35%
input power; 2.5 W
The specification of the preamplifier 20 is as follows:
output power; 2.5 W (less than 20 W by 9 dB)
input power; 0.156 W
gain; 12 dB
collector efficiency; 20%
Thus, we obtain the following results:
the power consumption of the Doherty amplifier is 20/0.35=57.1 W;
the power consumption of the preamplifier is 2.5/0.2=12.5 W; and
the power added efficiency of the common amplifier is (20−0.156)/(57.1+12.5)=27.5%.
As can be seen above, although the collector efficiency of the Doherty amplifier is enhanced as high as 35%, the total power efficiency as the common amplifier is reduced to 27.5%.
Besides, though it is also possible to serially connect the Doherty amplifiers, multi-stage amplifier configuration causes deterioration in the performance because the Doherty amplifier includes the phase converter 3 and the Doherty combiner 6 and its characteristics vary widely with frequency.